As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs will be on the order of 0.25 micron, and conventional dielectrics such as SiO.sub.2 and Si.sub.3 N.sub.4 might not be suitable because of small dielectric constants.
Chemical vapor deposited (CVD) Ta.sub.2 O.sub.5 films are considered to be very promising cell dielectrics layers, as the dielectric constant of Ta.sub.2 O.sub.5 is approximately three times that of Si.sub.3 N.sub.4. Proposed prior art capacitor constructions include the use of Ta.sub.2 O.sub.5 as a capacitor dielectric layer, in combination with an overlying predominately crystalline TiN electrode or other layer. However, diffusion relative to the tantalum layer is problematic in the resultant capacitor construction. For example, tantalum from the Ta.sub.2 O.sub.5 tends to undesirably out-diffuse from the dielectric layer. Further, materials from the adjacent conductive capacitor plates can diffuse into the tantalum layer. In either event, the dielectric properties of the Ta.sub.2 O.sub.5 layer are adversely affected in a less than predictable or an uncontrollable manner.